In paging and personal communication systems, radio carrier modulation techniques have evolved to use more complicated digital modulation methods, such as multi-level FM, in order to provide more sophisticated operational functions within limited bandwidth resources. Meanwhile, the design of demodulation circuits has evolved to demodulate these more complex modulations, while at the same time improving operational characteristics of the portable radios receiving the complex modulation. Some of the most important operational characteristics are signaling sensitivity, power drain, and cost. Analog demodulation techniques involving analog to digital circuits, peak and valley detectors, and threshold calculating circuitry have been used but suffer from large die area (which relates directly to cost, and typically also to power drain), and suffer from phase and amplitude distortion. In some new receiver designs used in portable radios, demodulation techniques that are a mixture of analog circuits, digital logic circuits, and a microprocessor circuit have been used to improve these characteristics. An example of such newer techniques is taught in U.S. Pat. No. 5,453,715, "Communication Device with Efficient Multi-level Digital Demodulator," issued on Sep. 26, 1995, which teaches a method of measuring time differences between zero crossings and measuring a direction of the zero crossings to accomplish demodulation of a multilevel frequency modulated signal. This technique relies on the conversion of a radio signal received at a carrier frequency to in-phase (I) and quadrature (Q) baseband signals that are manipulated by a small amount of front end analog circuitry that includes signal summing circuits and signal limiter circuits. The signal limiter circuits convert analog signals from the summing circuits to binary signals. The binary signals are then processed by a microprocessor to determine a time difference between successive zero crossings and a direction of a phase angle change of the analog signal at the zero crossings.
Another example of such newer techniques is taught in U.S. Pat. No. 5,633,895, "Communication Device with Synchronized Zero-Crossing Demodulator and Method," issued on May 27, 1997. This technique also relies on the conversion of a received signal at a carrier frequency to I and Q signals that are manipulated by a small amount of front end analog circuitry that includes signal summing circuits and signal limiter circuits. The signal limiter circuits convert analog signals from the summing circuits to binary signals. The binary signals are then processed by a microprocessor to determine a time difference between successive zero crossings and a direction of a phase angle change of the analog signal at the zero crossings. The microprocessor then uses the time differences between zero crossings and directions at zero crossings to generate a symbol clock synchronization signal to synchronize logic circuitry that is used to convert the binary signals into a symbol estimate.
While both of these techniques accomplish a sufficiently reliable demodulation of the received signal, they rely substantially on a microprocessor for determining the received symbol from the time between zero crossings and the phase angle direction at the zero crossings. The use of a microprocessor for this purpose requires significant program storage space and a continuous, significant portion of the available processing cycles whenever the radio is attempting to receive message. The use of the processing cycles typically results in additional power consumption.
Thus what is needed is a demodulation technique that efficiently accomplishes demodulation of multilevel digital FM signals, with less reliance on microprocessor resources.